Senior Staff Engineer - Physical Design

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Engineer - Physical Design based in India. This is a senior technical leadership opportunity focused on end-to-end physical implementation for advanced semiconductor and AI/HPC designs. You will lead complex block- and full-chip implementation activities from floorplanning through physical signoff and tape-out. The role has a strong emphasis on achieving demanding power, performance, area, timing, and reliability targets. You will collaborate closely with RTL, STA, DFT, package, and CAD teams to solve challenging implementation and signoff issues. The position also offers the opportunity to shape physical design methodologies, automation, and engineering best practices. You’ll work in a fast-moving, low-bureaucracy environment where deep technical expertise, ownership, and execution are highly valued. Based in Bengaluru with a remote-friendly setup, this role is suited to an experienced engineer who wants to make a direct impact on next-generation AI infrastructure. Lead physical design implementation: Own full-chip or block-level physical implementation from floorplanning and power planning through placement, CTS, routing, optimization, physical verification, and GDS signoff. Drive PPA and reliability optimization: Analyze and optimize timing, congestion, power, IR drop, electromigration, and signal integrity across advanced technology nodes. Manage signoff closure: Identify and resolve implementation issues and ensure high-quality closure across timing, power, area, and reliability requirements. Collaborate cross-functionally: Partner with RTL, DFT, STA, package, and CAD teams to address complex implementation, integration, and signoff challenges. Improve physical design methodologies: Develop and enhance implementation flows, automation scripts, tools, and methodologies to improve engineering efficiency and design quality. Support tape-out: Contribute to tape-out planning and execution while ensuring implementation milestones and signoff deliverables are completed with minimal schedule impact. Provide technical leadership: Participate in technical reviews, establish best practices, and proactively identify implementation bottlenecks and risks. Mentor engineers: Guide junior team members, share technical expertise, and contribute to the development of a strong physical design engineering culture. Drive innovation: Explore emerging approaches, including AI/ML-assisted design optimization, to improve physical implementation workflows and outcomes. Requirements: Experience: 12+ years of hands-on experience in ASIC/SoC physical design implementation. Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related technical discipline. EDA expertise: Strong proficiency with industry-standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, and StarRC. Physical design: Deep understanding of floorplanning, power planning, placement, clock-tree synthesis, routing, optimization, physical verification, and signoff. Timing & reliability: Strong knowledge of timing closure, low-power design techniques, signal integrity, IR/EM analysis, and physical verification. Advanced nodes: Experience working on advanced semiconductor technology nodes, with 7nm, 5nm, or 3nm experience preferred. Automation: Strong scripting capabilities in Tcl, Perl, and/or Python for flow development, automation, and methodology improvements. SoC integration: Experience with hierarchical and top-level SoC integration is desirable. Emerging technologies: Exposure to ML/AI-based physical design optimization is a plus. Advanced packaging: Knowledge of package-aware implementation and multi-die or chiplet architectures is advantageous. Problem-solving: Excellent debugging, analytical, and problem-solving skills, with the ability to tackle complex implementat