Senior Staff Engineer - Design Verification

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Engineer - Design Verification based in India. This is a senior technical leadership opportunity focused on verifying next-generation high-speed interconnect IPs and SoCs for demanding AI and HPC systems. You will define verification strategies and architectures for complex protocols including PCIe, CXL, Ethernet, and UCIe. The role combines hands-on engineering with technical leadership, covering UVM environments, coverage closure, assertions, debugging, and sign-off. You will work closely with architecture, design, and validation teams across sophisticated silicon development programs. The position also offers the opportunity to influence reusable verification frameworks and advance verification methodologies. As a senior contributor, you will mentor engineers while helping establish rigorous engineering standards across projects. The environment is fast-moving, technically ambitious, and focused on delivering production silicon for the rapidly expanding AI infrastructure market. Define and execute scalable, comprehensive verification strategies and plans for high-speed PCIe, CXL, Ethernet, and related IP and SoC subsystems. Architect and develop reusable, layered UVM testbenches, verification environments, agents, and components for complex protocol verification. Apply deep protocol expertise to verify PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and UCIe PHY and Adapter layers against demanding functionality and compliance requirements. Drive coverage-driven verification, including functional coverage, assertion-based verification, metrics analysis, coverage closure, and verification sign-off. Lead complex debug and root-cause analysis across simulation, emulation, prototyping, and silicon bring-up environments. Collaborate closely with design, architecture, validation, and other engineering teams to identify issues early and deliver robust, high-quality IP and SoC solutions. Establish verification best practices, methodologies, and reusable frameworks that can support multiple projects and tape-outs. Mentor junior and mid-level verification engineers, providing technical guidance and promoting strong verification discipline. Explore opportunities to incorporate AI/ML capabilities into verification workflows and improve engineering productivity. Contribute to performance, power-aware, hybrid, and other advanced verification initiatives as required. Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related technical discipline. 12+ years of professional experience in design verification, with substantial exposure to complex SoC and IP verification. Proven experience defining and implementing verification architectures for high-speed interconnect protocols and sophisticated semiconductor designs. Strong hands-on expertise in SystemVerilog, UVM, coverage-driven verification, and SystemVerilog Assertions (SVA). Deep practical knowledge of PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, or comparable high-speed protocols. Experience verifying UCIe PHY and Adapter layers is highly desirable. Strong understanding of SoC architecture, IP integration, high-speed interfaces, and verification methodologies. Demonstrated ability to lead complex debugging and problem-solving activities across simulation and hardware environments. Strong technical leadership skills, with the ability to influence engineering decisions and establish effective verification practices. Excellent communication and mentoring capabilities, with a collaborative and low-ego approach to working with cross-functional teams. Experience with emulation, prototyping, or hybrid verification platforms is a plus. Exposure to performance verification, power-aware verification, and AI/ML applications within verification workflows is advantageous. Experience developing verification f