Senior Staff Engineer – Static Timing Analysis (STA)

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior Staff Engineer – Static Timing Analysis (STA) based in India. This is a senior technical leadership opportunity focused on timing analysis and signoff for complex SoC designs and advanced semiconductor technologies. You will lead block-level and full-chip timing closure across multiple operating modes and corners using sophisticated MMMC methodologies. The role involves solving challenging timing issues alongside synthesis, CTS, place-and-route, extraction, and ECO teams. You will also help define timing constraints, drive optimization, and balance performance, power, and area requirements. A strong emphasis is placed on automation and methodology improvements that increase STA productivity and signoff efficiency. You will work within a fast-moving, highly technical environment where ownership, engineering depth, and practical execution are valued. This is an opportunity to contribute directly to advanced AI/HPC silicon infrastructure and help drive successful tapeout of complex designs. Lead block-level and full-chip Static Timing Analysis (STA) activities, covering setup, hold, recovery, removal, and noise analysis. Drive timing closure across multiple modes and corners using MMMC (Multi-Mode Multi-Corner) methodologies. Analyze, debug, and resolve complex timing violations in collaboration with synthesis, CTS, place-and-route, extraction, and ECO teams. Define and validate timing constraints, including SDC generation, timing exceptions, clock definitions, and related timing requirements . Perform timing signoff using industry-standard STA tools and established signoff methodologies. Drive ECO implementation and timing optimization while balancing performance, power, and area (PPA) objectives. Collaborate with implementation and signoff teams to achieve robust timing convergence and support timely tapeout execution. Contribute to STA automation, methodology enhancements, flow optimization, and productivity initiatives. Improve the efficiency and consistency of timing analysis and signoff processes through scripting and workflow optimization. Support successful timing closure across complex SoC designs while maintaining high signoff quality across all relevant operating conditions. Requirements 10+ years of professional experience in STA, timing closure, physical design signoff, or closely related semiconductor engineering roles. Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI , or a related technical discipline. Strong understanding of STA concepts, including OCV, AOCV, POCV, signal integrity/noise analysis, clocking methodologies, and timing exceptions . Hands-on experience with Synopsys PrimeTime and advanced timing signoff flows. Strong understanding of the semiconductor implementation flow, including synthesis, CTS, place-and-route, extraction, and ECO implementation . Proven ability to drive timing closure across complex designs and multiple modes and corners. Strong scripting and automation capabilities using Tcl, Perl, Python, Shell , or similar languages. Experience troubleshooting complex timing problems and collaborating effectively with cross-functional implementation teams. Experience with advanced-node technologies such as 7nm, 5nm, or below is highly desirable. Exposure to low-power design methodologies, including UPF/CPF and power-aware STA , is a plus. Experience with full-chip timing convergence and successful tapeout execution for large SoC designs is advantageous. Strong analytical and problem-solving capabilities, with the ability to work independently and take ownership of complex technical challenges. Excellent cross-functional communication and collaboration skills, combined with a hands-on, results-oriented mindset. Benefits Remote work option in India , with the opportunity to work in a hybrid/on-site setup in Bengaluru when applicable. Op